Research Associate in Electronic Engineering

Job Description:
The job involves the design and development of a software tool for automatically generating Verilog HDL hardware implementations of approximate arithmetic components and circuits (e.g. adders, multipliers, etc). This tool will be required to interface into a commercial HDL-based FPGA tool flow.

Job Requirements:

  • Education: Master’s degree in Computer Science or Electrical and Electronic Engineering.
  • Skills: Demonstrated programming knowledge in C, C++, Python, etc.
  • Excellent written and verbal English communication skills.
  • A knowledge of Verilog HDL/ VHDL would be an advantage.

Application Procedure:
Interested applicants please attach your full CV (including educational background, research and work experience(s), list of publications and highlighting previous relevant experience), the names and contacts (including email addresses) of 3 character referees, and all relevant academic certificates to Assoc Prof Douglas Maskell (
We regret that only shortlisted candidates will be notified.

Applications close when positions is filled.